1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a non-volatile memory. In particular, the present invention relates to a semiconductor integrated circuit capable of reducing a write cycle of a write command to one time when 16 bits data is written in a write mode in units of 8 bits.
2. Description of the Related Art
FIG. 1 is a block diagram showing a configuration of a conventional semiconductor integrated circuit 1 having a non-volatile memory. As shown in FIG. 1, the conventional semiconductor integrated circuit 1 comprises an input buffer 2 for controlling data input and/or output, having 16 external data pins DQ1 to DQ15, and a switch portion 3 is connected to the input buffer 2. To the switch portion 3, the least significant address [A-1] of a write address PA (program address) is input via an external address pin (not shown). In addition, a data latch portion 4 for saving input data for a short time is provided so as to be connected to the switch portion 3; a write circuits 5 are provided so as to be connected to the data latch portion 4; and there are provided memory cells 6 (refer to FIG. 5) of an non-volatile memory so as to be connected to the write circuits 5. In addition, 16 latches L0 to L15 are provided at the data latch portion 4. Each latch holds 1-bit data until a new signal has been input.
To the input buffer 2, data is externally input via the external data pins DQ1 to DQ15, and the data is input from the input buffer 2 to the switch portion 3. The switch portion 3 distributes the input data into latches selected from latches L0 to L15 of the data latch portion 4 based on a logical value of the least significant address [A-1] of the write address PA.
In addition, a data fetch control portion 7 is provided so as to be connected to the data latch portion 4, and a command system circuit 8 is provided so as to be connected to the data fetch control portion 7. A write enable signal WE# for controlling write operation of the semiconductor integrated circuit 1 is input to the data fetch control portion 7. Further, a reset circuit 9 for resetting output data of each latch of the data latch portion 4 is provided so as to be connected to the data latch portion 4. To the reset circuit 9, the least significant address [A-1] of the write address PA and a write mode switching signal BYTE# for switching a write mode of the semiconductor integrated circuit 1 are input.
The conventional semiconductor integrated circuit 1 enables operation in two modes, i.e., a xe2x80x9cx 8 modexe2x80x9d for writing data in units of 8 bits and a xe2x80x9cx 16 modexe2x80x9d for writing data in units of 16 bits. In addition, the circuit performs switching by the write mode switching signal BYTE#. For example, in a case where a logical value of the write mode switching signal BYTE# is xe2x80x9cLxe2x80x9d, the xe2x80x9cx 8 modexe2x80x9d is selected, and in a case where a logical value of the write mode switching signal BYTE# is xe2x80x9cHxe2x80x9d, the xe2x80x9cx 16 modexe2x80x9d is selected.
Now, operation of the semiconductor integrated circuit 1 will be described. FIG. 2 is a timing chart showing a 16 bits data write operation in the xe2x80x9cx 8 modexe2x80x9d in the conventional semiconductor integrated circuit 1. As shown in FIGS. 1 and 2, a logical value of the write mode switching signal BYTE# to be input to the reset circuit 9 is xe2x80x9cLxe2x80x9d, and the xe2x80x9cx 8 modexe2x80x9d is selected as a write mode. Next, the write data PD (program data) is input to the input buffer 2 via the external data pins DQ0 to DQ7. At this time, in a case where the logical value of the least significant address [A-1] of the write address PA to be input to the switch portion 3 is xe2x80x9cLxe2x80x9d, the write data PD is distributed to latches L0 to L7 that configure a lower order side of the data latch portion 4 by the switch portion 3. The input data is then latched in the latches L0 to L7. In addition, when the least significant address [A-1] of the write address PA is xe2x80x9cHxe2x80x9d, the write data PD is distributed to latches L8 to L15 that configure an upper order side of the data latch portion 4 by the switch portion 3. The input data is then latched in the latches L8 to L15.
When the logical value of the least significant address [A-1] is xe2x80x9cLxe2x80x9d, an upper order side reset signal RST1 is outputted from the reset circuit 9 to reset terminals R of the latches L8 to L15 that configure the upper order side of the data latch portion 4. The output values of these latches for unused 8 bits are set to xe2x80x9cFFhxe2x80x9d by resetting the latches L8 to L15. On the other hand, when the logical value of the least significant address [A-1] is xe2x80x9cHxe2x80x9d, a lower order side reset signal RST2 is outputted to the reset terminals R of the latches L0 to L7 that configure the lower order side of the data latch portion 4. The output values of these latches for unused 8 bits are set to xe2x80x9cFFhxe2x80x9d by resetting the latches L0 to L7. That is, xe2x80x9cHxe2x80x9d of xe2x80x9cFFhxe2x80x9d denotes a hexadecimal notation, and xe2x80x9cFFhxe2x80x9d denotes xe2x80x9c11111111xe2x80x9d in a binary notation. Thus, all the output value of latches for the 8 bits are set to xe2x80x9c1xe2x80x9d.
In addition, in the semiconductor integrated circuit 1, a write command for performing writing into a non-volatile memory, for example, a write command [xe2x80x9cAAhxe2x80x9dxe2x80x94xe2x80x9c55hxe2x80x9dxe2x80x94xe2x80x9cA0hxe2x80x9d xe2x80x94PD] is input to the command system circuit 8, whereby a write flag signal from the command system circuit 8 is output to the data fetch control portion 7. On the other hand, a 4-cycle write enable signal WE# is input to the data fetch control portion 7. Then, the data fetch control portion 7 outputs to the data latch portion 4 a latch flag STDATA (PA, PD latch flag) that is a data fetch pulse in synchronism with the write enable signal WE#. The data fetch pulse is a one-shot pulse having a protrusive pulse shape.
Hereinafter, description will be given in more detail. FIG. 3 is a partially enlarged view of the timing chart of the semiconductor integrated circuit 1 shown in FIG. 2. As shown in FIG. 3, a write command and a write address PA are input to the semiconductor integrated circuit 1 in synchronism with the write enable signal WE#, whereby the write data PD (program data) and write address PA corresponding to the protrusive pulse of the latch flag STDATA of the write data PD and write address PA are input to the data latch portion 4. After holding these data, the data latch portion 4 automatically generates a write pulse internally, thereby automatically performing a write operation for memory cells 6 of a non-volatile memory.
For example, in the case where a write command is [xe2x80x9cAAhxe2x80x9dxe2x80x94xe2x80x9c55hxe2x80x9dxe2x80x94xe2x80x9cA0hxe2x80x9dxe2x80x94PD], and a write address PA is [xe2x80x9c555hxe2x80x9dxe2x80x94xe2x80x9c2AAhxe2x80x9dxe2x80x94xe2x80x9c555hxe2x80x9dxe2x80x94PA], the write command [xe2x80x9cAAhxe2x80x9dxe2x80x94xe2x80x9c55xe2x80x9dxe2x80x94xe2x80x9cA0hxe2x80x9dxe2x80x94PD] and the write address [xe2x80x9c555hxe2x80x9dxe2x80x94xe2x80x9c2AAhxe2x80x9dxe2x80x94xe2x80x9c555hxe2x80x9dxe2x80x94PA] are input to the semiconductor integrated circuit 1 in synchronism with the write enable signal WE#, thereby holding the write data PA and write data PD corresponding to the protrusive pulse of the latch flag STDATA. Then, a write pulse is automatically generated internally, thereby automatically performing a write operation for the non-volatile memory. At this time, the write enable signal WE# is about 1 microsecond (xcexcs) at one cycle. Thus a time of 4 microsecondsis required to cause the write data PD and write address PA to be input to the data latch portion 4. Further, a time of 8 microseconds is required to cause these data to be transferred from the data latch portion 4 to the memory cells 6 of the non-volatile memory.
FIG. 4 is a flow chart showing a write operation of a conventional semiconductor integrated circuit 1. As shown in FIG. 4, in the semiconductor integrated circuit 1, a write command is input to a command system circuit 8 (step S41); whereby the write data PD and the write address PA are latched in the data latch portion 4 (step S42); write verify processing (write check processing) is performed for the memory cell 6 selected by the latched write address PA; the write data PD is compared with the memory cell data read out from the memory cell 6 (step S43); and if writing fails (if NG at the step S43), writing (step S44) is performed, and then, the write verify processing (write check processing) (step S43) is performed again. Such write processing and write verify processing (write check processing) are continuously performed until write check processing has been omitted (xe2x80x9cVerify Passxe2x80x9d). On the other hand, if writing is successful (if OK at the step S43), write operation is terminated (step S45).
FIG. 5 is a block diagram showing a write operation in the xe2x80x9cx 8 modexe2x80x9d for the lower order side input and/or output pins I/O 0 to I/O 7 (not shown) of the non-volatile memory. In the conventional semiconductor integrated circuit 1 having a non-volatile memory, as shown in FIG. 5, in the case where writing operation into the lower order side input and/or output pins I/O 0 to I/O 7 (not shown) of the non-volatile memory is performed after the xe2x80x9cx 8 modexe2x80x9d has been selected, the write data PD is divided into first write data PD1 and second write data PD2. The first write data PD1 is first input to an input buffer 2 via the external data pins DQ0 to DQ7.
At this time, in the case where the logical value of the least significant address [A-1] of the write address PA input to the switch portion 3 is xe2x80x9cLxe2x80x9d, the input first write data PD1 is distributed by means of the switch portion 3 in the latches L0 to L7 that configure the lower order side of the data latch portion 4. The fetched data is then latched by the latches L0 to L7.
At this time, as described above, latches L8 to L15 that configure the upper side of the data latch portion 4 are forcibly set to write data xe2x80x9c1xe2x80x9d by means of the upper side reset signal RST1. The write data xe2x80x9c1xe2x80x9d indicates a state in which data has already been written, and thus, the latches L8 to L15 are not targeted to be written data in write operation, that is, the latches L8 to L15 are xe2x80x9cNo Carexe2x80x9d. Therefore, the latches L8 to L15 can pass the write verify processing. As a result, their output value is xe2x80x9cFFhxe2x80x9d.
Then, the write data PD is written into the lower order side input and/or output pins I/O 0 to I/O 7 of the non-volatile memory via a write circuit 5. Further, the values of the upper order side input and/or output pin I/O 8 to I/O 15 (not shown) are set to xe2x80x9cFFhxe2x80x9d, and thus, write check processing is omitted (xe2x80x9cVerify passxe2x80x9d).
Then, the second write data PD2 is written into the input and/or output pins I/O8 to I/O15 at the upper side of the non-volatile memory. FIG. 6 is a block diagram showing a write operation in the xe2x80x9cx 8 modexe2x80x9d for the upper order side input and/or output pins I/O 8 to I/O 15 in the conventional semiconductor circuit 1. As shown in FIG. 6, unlike the write operation in the xe2x80x9cx 8 modexe2x80x9d for the lower order side input and/or output pins I/O shown in FIG. 5, in the case where writing into the upper order side input and/or output pins I/O 8 to I/O 15 of the non-volatile memory is performed after the xe2x80x9cx 8 modexe2x80x9d has been selected, the second write data PD2 is input to the input buffer 2 via the external data pins DQ0 to DQ7.
At this time, the logical value of the least significant address [A-1] of the write address PA is xe2x80x9cHxe2x80x9d. Thus, the second write data PD2 is distributed by switch portion 3 into the latches L8 to L15 that configure the upper order side of the data latch portion 4, and is latched in the latches L8 to L15. At this time, the output values of the latches L0 to L7 that configure the lower order side of the data latch portion 4 are forcibly set to xe2x80x9cFFhxe2x80x9d by means of the lower order side reset signal RST2.
Then, the second write data PD2 is written into the upper order side input and/or output pins I/O 8 to I/O 15 of the non-volatile memory via the write circuit 5. For the lower order side input and/or output pins I/O 0 to I/O 7 of the non-volatile memory, their values are set to xe2x80x9cFFhxe2x80x9d, and thus, write check processing is omitted (xe2x80x9cVerify Passxe2x80x9d).
However, in the aforementioned conventional semiconductor integrated circuit, there are the problems described below. As shown in FIG. 2, in the conventional semiconductor integrated circuit 1, in the case where the xe2x80x9cx 8 modexe2x80x9d is selected as a write operation, only 8-bits write data can be fetched at one write cycle of a write command. Therefore, in the case where 16-bits write data PD is fetched in the xe2x80x9cx 8 modexe2x80x9d, it is required to execute two command write cycles. Thus, there is a problem that a write operation speed in the semiconductor integrated circuit 1 is lowered.
That is, it is required to set the logical value of the least significant address [A-1] of the write address PA to xe2x80x9cLxe2x80x9d; and write the first write data PD1 into the lower order side input and/or output pins I/O 0 to I/O 7 at a first write cycle of a write command; and then, set the logical value of the least significant address [A-1] of the write address PA to xe2x80x9cHxe2x80x9d, and write the second write data PD2 into the upper order side input and/or output pins I/O 8 to I/O 15 at a second write cycle of a write command. At this time, as shown in FIGS. 2 and 3, one write cycle of a write command requires a time of about 12 microseconds, and thus, two write cycle of a write command require a time of about 24 microseconds.
In addition, in the conventional semiconductor integrated circuit having a non-volatile memory, there exists a mode capable of reducing a write command called a continuous mode. However, in the continuous mode as well, only a write command can be simplified. In the case where an operation for writing 16-bits data in the xe2x80x9cx 8 modexe2x80x9d is performed in the continuous mode, there is a problem that two write operations are required.
Further, Japanese Patent Application Laid-open No. 2-140853 discloses a bus width converting circuit for connecting a CPU for inputting and/or outputting data in a 16-bits bus width to a peripheral device for inputting and/or outputting data in a 8-bits bus width. In this bus width converting circuit, a counter circuit is provided for the purpose of speeding up a data transfer speed between the CPU and the peripheral device. 16-bits data input from the CPU is divided into 8 bits to be outputted to the peripheral device in accordance with an instruction from this counter circuit. In addition, 8-bits data input from the peripheral device is integrated into 16 bits to be outputted to the CPU.
However, in this bus width converting circuit, there is a problem that a circuit configuration becomes complicated because a counter circuit is required. In addition, a counting system of this counter circuit is based on a counter system of xe2x80x9c00xe2x80x9d (0 byte hold)xe2x80x94xe2x80x9c01xe2x80x9d (1 byte hold)xe2x80x94xe2x80x9c10xe2x80x9d (CPU transfer). Thus, there may be a case in which, when xe2x80x9c01xe2x80x9d (1 bytehold) is counted up to xe2x80x9c10xe2x80x9d (CPU transfer), a wiring delay occurs, and a state of xe2x80x9c01xe2x80x9d (1 byte hold)xe2x80x94xe2x80x9c00xe2x80x9d (0 byte hold)xe2x80x94xe2x80x9c10xe2x80x9d (CPU transfer) occurs. Thus, there may occur a malfunction that 0 byte is mistakenly fetched when the count value is xe2x80x9c00xe2x80x9d (0 byte hold).
It is an object of the present invention to provide a semiconductor integrated circuit capable of reducing the number of write cycle of a write command to one when [mxc3x97n] bits data is written in a write mode xe2x80x9cx m modexe2x80x9d, and capable of operating with high reliability.
A semiconductor integrated circuit comprises: a non-volatile memory; a data latch portion having [mxc3x97n] latches, holding input write data in [mxc3x97n] bits length, and outputting the write data to the non-volatile memory in batch; and a data fetch control portion for generating a data fetch pulse for fetching the write data into each latch of the n separate parts based on the logical value of the least significant address of write addresses in one write cycle of a write command of writing the write data into the non-volatile memory in xe2x80x9cx m modexe2x80x9d,wherein the data fetch control portion repeats a write data fetch command n times when the write command is input in the write cycle of the write command, and inputs the write data of [mxc3x97n] bits in length to the data latch portion for each m bits in xe2x80x9cx m modexe2x80x9d, and the data latch portion outputs the write data of [mxc3x97n] bits in length to the non-volatile memory in batch.
In the present invention, in the case where [mxc3x97n] bits data is written in m-bits unit write mode, a number of write cycle of a write command can be reduced to one. As a result, the write time can be reduced.
In addition, the semiconductor integrated circuit comprises: an input buffer having external data pins; and a switch portion connected to the input buffer, wherein the write data is input from the external data pins, and the write data is distributed into each latch of the n separate parts of the data latch portion through switch control performed by the switch portion via the input buffer.
In the semiconductor integrated circuit of the present invention, there is eliminated a reset circuit for resetting the output signal of each latch at the data latch portion that has been necessary, and a circuit configuration can be simplified.
Furthermore, the semiconductor integrated circuit comprises a write circuit, wherein the fetched write data of [mxc3x97n] bits in length input to the data latch portion is written into the non-volatile memory in batch in [mxc3x97n] bits via the write circuit. Still furthermore, m may be 8 and n may be 2, and the data fetch pulse may be formed in a one-shot pulse shape.